HIGH PERFORMANCE OF CODING AND DECODING PROCESS FOR DATA COMPRESSION USING VARIABLE IN LENGTH CODING

MAAN  HAMEED; AHMED LATEEF  HAMEED; NASEER ALWAN  HUSSEIN

doi:10.26682/csjuod.2023.26.2.37

MAAN HAMEED *Ministry of Water Resources, State Commission for Reservoirs and Dams, Diyala- Iraq
AHMED LATEEF HAMEED **Diyala Education Directorate, Ministry of Education, Diyala- Iraq
NASEER ALWAN HUSSEIN

DOI: https://doi.org/10.26682/csjuod.2023.26.2.37

Keywords: Data compression, Symbols, Encoding, Delays, Decoding

Abstract

Data compression using Huffman coding refers to decreasing the quantity of data without decreasing the quality of original file. Besides that, it can retrieve original data in decompression process without losing any details. In this research, an 9bit/8bit encoding and decoding process divide the block design. The input transmission code consists of 9-bit which are variable in length coding and can be suitable for high-speed applications. Coding and decoding blocks were designed separately. The encoder module gets the 9-bit data used as input and delivers the 8-bit coded-output from encoder design. this output data used as input to the decoder module to get the 8-bit as output form decoder design. In this research, the proposed design includes encoder and decoder were achieved Compression Ratio up to 52% from original data size and saving percentage up to 47.95%. The suggested design was implemented by using ASIC and FPGA design methodologies to execute the compression and decompression architectures. The architecture of coding and decoding process has been created using Verilog HDL language. Quartus II 11.1 Web Edition (32-Bit). In addition, simulated using ModelSim-Altera 10.0c (Quartus II 11.1) Starter Edition. And it is implemented using Altera FPGA (DE2) for real time implementation. Finally, all of the blocks were combined together to have an integrated system.

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